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[X86] Add RET-hardening Support to mitigate Load Value Injection (LVI)
authorScott Constable <scott.d.constable@intel.com>
Fri, 3 Apr 2020 17:58:38 +0000 (10:58 -0700)
committerCraig Topper <craig.topper@intel.com>
Fri, 3 Apr 2020 19:08:34 +0000 (12:08 -0700)
commitf95a67d8b8a8cec326ee4a7e8427b779936d100a
tree2ca001a2f27fb17147c560be8c1a4962327833fbtree | snapshot
parentba87430cadb2d5d0ee8e4b75101d7abcf6b321bfcommit | diff
[X86] Add RET-hardening Support to mitigate Load Value Injection (LVI)

Adding a pass that replaces every ret instruction with the sequence:

pop <scratch-reg>
lfence
jmp *<scratch-reg>

where <scratch-reg> is some available scratch register, according to the
calling convention of the function being mitigated.

Differential Revision: https://reviews.llvm.org/D75935
llvm/lib/Target/X86/CMakeLists.txt diff | blob | history
llvm/lib/Target/X86/X86.h diff | blob | history
llvm/lib/Target/X86/X86LoadValueInjectionRetHardening.cpp [new file with mode: 0644] blob
llvm/lib/Target/X86/X86TargetMachine.cpp diff | blob | history
llvm/test/CodeGen/X86/O0-pipeline.ll diff | blob | history
llvm/test/CodeGen/X86/O3-pipeline.ll diff | blob | history
llvm/test/CodeGen/X86/lvi-hardening-ret.ll [new file with mode: 0644] blob
Domain: System / Toolchain;