[RISC-V] Simplify codegen for div/mod (#96068)
authorTomasz Sowiński <tomeksowi@gmail.com>
Thu, 21 Dec 2023 01:15:32 +0000 (02:15 +0100)
committerGleb Balykov/Advanced System SW Lab /SRR/Staff Engineer/Samsung Electronics <g.balykov@samsung.com>
Tue, 26 Dec 2023 08:37:03 +0000 (11:37 +0300)
commitf944085187b132939771982ac9dddf9ba0cf8c59
tree3f2294bb2b872f6ac17641ee34379786cc601365
parent1ef8b73ac3214f0c5dacfa64e0bb6ea7a791589d
[RISC-V] Simplify codegen for div/mod (#96068)

* [RISC-V] Simplify codegen for div/mod

After #82924 some testing can be simplified. Change analogous to #85140.

* [RISC-V] Remove sign-extending for divuw/remuw

These instructions take only the lower 32 bits of the argument registers anyway.

* [RISC-V] Give genCodeForDivMod a haircut.

* [RISC-V] Remove TypeGet() from genActualType as per review comments in #95673
src/coreclr/jit/codegenriscv64.cpp
src/coreclr/jit/lsrariscv64.cpp