iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126
authorGeetha Sowjanya <geethasowjanya.akula@cavium.com>
Fri, 23 Jun 2017 13:34:36 +0000 (19:04 +0530)
committerWill Deacon <will.deacon@arm.com>
Fri, 23 Jun 2017 16:58:04 +0000 (17:58 +0100)
commitf935448acf462c26142e8b04f1c8829b28d3b9d8
tree7516f4e4d39117e80be3b2859451725faded8271
parent99caf177f6fd3e67575f6ce05b36e8e041bcef60
iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126

Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq
lines for gerror, eventq and cmdq-sync.

New named irq "combined" is set as a errata workaround, which allows to
share the irq line by register single irq handler for all the interrupts.

Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Geetha sowjanya <gakula@caviumnetworks.com>
[will: reworked irq equality checking and added SPI check]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Documentation/arm64/silicon-errata.txt
Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
drivers/acpi/arm64/iort.c
drivers/iommu/arm-smmu-v3.c