projects / profile / ivi / kernel-x86-ivi.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 93f5f7f) | patch
agp/intel: Fix cache control for Sandybridge
authorZhenyu Wang <zhenyuw@linux.intel.com>
Fri, 27 Aug 2010 03:08:57 +0000 (11:08 +0800)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 7 Sep 2010 10:16:43 +0000 (11:16 +0100)
commitf8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337
tree9211554f0542ce636aa1f14ffe58cfa832efa04dtree | snapshot
parent93f5f7f1249e76a5e8afbdab53f90b10c41fdb61commit | diff
agp/intel: Fix cache control for Sandybridge

Sandybridge GTT has new cache control bits in PTE, which controls
graphics page cache in LLC or LLC/MLC, so we need to extend the mask
function to respect the new bits.

And set cache control to always LLC only by default on Gen6.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/char/agp/intel-agp.c diff | blob | history
drivers/char/agp/intel-gtt.c diff | blob | history
drivers/gpu/drm/i915/i915_gem.c diff | blob | history
include/linux/intel-gtt.h [new file with mode: 0644] blob
Domain: System / Uncategorized;