[MachineCombiner] Extend reassociation logic to handle inverse instructions
authorAnton Sidorenko <anton.sidorenko@syntacore.com>
Fri, 14 Oct 2022 13:20:43 +0000 (16:20 +0300)
committerAnton Sidorenko <anton.sidorenko@syntacore.com>
Wed, 7 Dec 2022 10:50:28 +0000 (13:50 +0300)
commitf8ed7093452aabd71650a3bb5dbca942815f9563
treeeb599f4d71aa5dca2c54da7a4badfdaaa0b798b6
parent0abf513d0f3ac7f13694ea5376f669c03f8b7600
[MachineCombiner] Extend reassociation logic to handle inverse instructions

Machine combiner supports generic reassociation only of associative and
commutative instructions, for example (A + X) + Y => (X + Y) + A. However, we
can extend this generic support to handle patterns like
(X + A) - Y => (X - Y) + A), where `-` is the inverse of `+`.
This patch adds interface functions to process reassociation patterns of
associative/commutative instructions and their inverse variants with minimal
changes in backends.

Differential Revision: https://reviews.llvm.org/D136754
32 files changed:
llvm/include/llvm/CodeGen/TargetInstrInfo.h
llvm/lib/CodeGen/TargetInstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.h
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.h
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrInfo.h
llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
llvm/test/CodeGen/AArch64/arm64-rev.ll
llvm/test/CodeGen/AArch64/machine-combiner.ll
llvm/test/CodeGen/AArch64/sqrt-fastmath.ll
llvm/test/CodeGen/PowerPC/machine-combiner.ll
llvm/test/CodeGen/RISCV/machine-combiner.ll
llvm/test/CodeGen/X86/avx512-mask-op.ll
llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll
llvm/test/CodeGen/X86/avx512fp16-machine-combiner.ll
llvm/test/CodeGen/X86/avx512fp16-mscatter.ll
llvm/test/CodeGen/X86/avx512vl-intrinsics.ll
llvm/test/CodeGen/X86/horizontal-sum.ll
llvm/test/CodeGen/X86/machine-combiner-int-vec.ll
llvm/test/CodeGen/X86/machine-combiner.ll
llvm/test/CodeGen/X86/madd.ll
llvm/test/CodeGen/X86/masked_gather_scatter.ll
llvm/test/CodeGen/X86/mul-constant-i64.ll
llvm/test/CodeGen/X86/pr46877.ll
llvm/test/CodeGen/X86/sqrt-fastmath.ll
llvm/test/CodeGen/X86/umulo-128-legalisation-lowering.ll
llvm/test/CodeGen/X86/x86-interleaved-access.ll