media: dt-bindings: tegra: Update csi data-lanes to maximum 8 lanes
authorSowjanya Komatineni <skomatineni@nvidia.com>
Fri, 11 Dec 2020 17:02:40 +0000 (18:02 +0100)
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Mon, 4 Jan 2021 12:02:44 +0000 (13:02 +0100)
commitf8c9dd2b826d8f1c23b8e86d5e4135a668a7bdd4
treea84752dd50b73a159939b363036fbc9afcb1dfa1
parent8f81888bec5c0a5f27083ca58024fb80fe902393
media: dt-bindings: tegra: Update csi data-lanes to maximum 8 lanes

Tegra VI/CSI hardware don't have native 8 lane CSI RX port.

But x8 capture can be supported by using consecutive x4 ports
simultaneously with HDMI-to-CSI bridges where source image is split
on to two x4 ports.

This patch updates dt-bindings for csi endpoint data-lane property
with maximum of 8 lanes.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt