[SDAG] Allow scalable vectors in ComputeNumSignBits
authorPhilip Reames <preames@rivosinc.com>
Fri, 18 Nov 2022 17:57:42 +0000 (09:57 -0800)
committerPhilip Reames <listmail@philipreames.com>
Fri, 18 Nov 2022 18:50:06 +0000 (10:50 -0800)
commitf8c63a7fbf50fb5883bd566c7539d0ac18c7700f
tree89202544d0e14bc3d2c1df521d9b3daff443ca08
parent625f08da730fc5e763a339f705e5bfefe71eb7e7
[SDAG] Allow scalable vectors in ComputeNumSignBits

This is a continuation of the series of patches adding lane wise support for scalable vectors in various knownbit-esq routines.

The basic idea here is that we track a single lane for scalable vectors which corresponds to an unknown number of lanes at runtime. This is enough for us to perform lane wise reasoning on many arithmetic operations.

Differential Revision: https://reviews.llvm.org/D137141
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
llvm/test/CodeGen/AArch64/sve-smulo-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll