x86/acpi/cstate: Add Zhaoxin processors support for cache flush policy in C3
authorTony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Tue, 18 Jun 2019 08:37:29 +0000 (08:37 +0000)
committerThomas Gleixner <tglx@linutronix.de>
Sat, 22 Jun 2019 09:45:58 +0000 (11:45 +0200)
commitf8c0e061cb83bd528ff0843e717bcebc846d4838
treea394087b89b21832b92d37728faf51659cfee2ae
parent773b2f30a3fc026f3ed121a8b945b0ae19b64ec5
x86/acpi/cstate: Add Zhaoxin processors support for cache flush policy in C3

Same as Intel, Zhaoxin MP CPUs support C3 share cache and on all
recent Zhaoxin platforms ARB_DISABLE is a nop. So set related
flags correctly in the same way as Intel does.

Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: "hpa@zytor.com" <hpa@zytor.com>
Cc: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
Cc: "rjw@rjwysocki.net" <rjw@rjwysocki.net>
Cc: "lenb@kernel.org" <lenb@kernel.org>
Cc: David Wang <DavidWang@zhaoxin.com>
Cc: "Cooper Yan(BJ-RD)" <CooperYan@zhaoxin.com>
Cc: "Qiyuan Wang(BJ-RD)" <QiyuanWang@zhaoxin.com>
Cc: "Herry Yang(BJ-RD)" <HerryYang@zhaoxin.com>
Link: https://lkml.kernel.org/r/a370503660994669991a7f7cda7c5e98@zhaoxin.com
arch/x86/kernel/acpi/cstate.c