perf/x86/intel: Add Ivy Bridge-EP uncore IRP box support
authorYan, Zheng <zheng.z.yan@intel.com>
Thu, 31 Oct 2013 05:36:55 +0000 (13:36 +0800)
committerIngo Molnar <mingo@kernel.org>
Wed, 6 Nov 2013 11:34:31 +0000 (12:34 +0100)
commitf891d8cfb8372eb9cfe9d0d4ca61c75bafeaae37
treeae3b266e611589af98fddb11b5c8d074a6a657c5
parentd1e8f4a8365d16fd179cb8cad5b4d20aafd0a695
perf/x86/intel: Add Ivy Bridge-EP uncore IRP box support

Unlike other uncore boxes, IRP boxes live in PCI buses with no UBOX
device. For PCI bus without UBOX device, we find the next bus that
has UBOX device and use its 'bus to socket' mapping.

Besides the counter/control registers in IRP boxes are not properly
aligned.

Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: eranian@google.com
Cc: "Yan Zheng" <zheng.z.yan@intel.com>
Link: http://lkml.kernel.org/r/1383197815-17706-2-git-send-email-zheng.z.yan@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/kernel/cpu/perf_event_intel_uncore.c