[X86] Connect the default fpsr and dirflag clobbers in inline assembly to the registe...
authorCraig Topper <craig.topper@intel.com>
Tue, 5 Feb 2019 06:13:06 +0000 (06:13 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 5 Feb 2019 06:13:06 +0000 (06:13 +0000)
commitf86eb00f122f3524e256b9a2059a3b37a25583ff
tree9a5400ed6b9de1566b3bac4ed73bb48922638293
parent73f499771f84ffed1c2a7fb19593d05f3cd91ffd
[X86] Connect the default fpsr and dirflag clobbers in inline assembly to the registers we have defined for them.

Summary:
We don't currently map these constraints to physical register numbers so they don't make it to the MachineIR representation of inline assembly.

This could have problems for proper dependency tracking in the machine schedulers though I don't have a test case that shows that.

Reviewers: rnk

Reviewed By: rnk

Subscribers: eraman, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D57641

llvm-svn: 353141
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86RegisterInfo.td
llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll [new file with mode: 0644]