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[RISCV] Define vector vfwadd/vfwsub intrinsics.
authorHsiangkai Wang <kai.wang@sifive.com>
Sat, 19 Dec 2020 15:12:18 +0000 (23:12 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Sun, 20 Dec 2020 09:39:13 +0000 (17:39 +0800)
commitf86e61d8862f5d2d6a1c5e5b566a58e330ff2e3f
tree87c0563bfcf44d96347698bb88780037c16e07f9tree | snapshot
parentbd576ac8d4b11566b41b778915cdbd50786a0f71commit | diff
[RISCV] Define vector vfwadd/vfwsub intrinsics.

Define vector vfwadd/vfwsub intrinsics and lower them to V
instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>
Differential Revision: https://reviews.llvm.org/D93583
llvm/include/llvm/IR/IntrinsicsRISCV.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td diff | blob | history
llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll [new file with mode: 0644] blob
Domain: System / Toolchain;