drm/i915: Allow concurrent read access between CPU and GPU domain
authorChris Wilson <chris@chris-wilson.co.uk>
Tue, 10 Apr 2012 10:52:50 +0000 (11:52 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 12 Apr 2012 19:14:10 +0000 (21:14 +0200)
commitf84131905b9b3b02b1c5061c0720e503c8d22778
tree405f14482ee9b64ac8f0a95e90ae4a87b06b7e3a
parent211c568bc6a1ebd51e35724f6d733e76717ce368
drm/i915: Allow concurrent read access between CPU and GPU domain

Similar to allowing a buffer to be simultaneously read by the GPU and
through the GTT, we wish to allow readback of the pages through the CPU
domain whilst they are also being read by the GPU. Domain coherency
is managed by allowing multiple readers, but only a single writer.

This is used by mesa for its program cache which it may search for every
new program every frame and then renews should it need to add. During
renewal, mesa copies the program bo currently executing through a CPU
mapping onto the new bo. This patch allows the search and that copy to
proceed without causing a stall on the current batch.

Testcase: i-g-t/tests/gem_cpu_concurrent_blit
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_gem.c