clk: imx: fix pll clock parents
authorDong Aisheng <aisheng.dong@nxp.com>
Wed, 8 Jun 2016 14:33:36 +0000 (22:33 +0800)
committerShawn Guo <shawnguo@kernel.org>
Sun, 12 Jun 2016 13:21:41 +0000 (21:21 +0800)
commitf83d31635cd65dd10eddaac1809b9e400d385d43
tree16114810176382e8255a504e5f41d58e905fbc44
parent147947549507fbbdbb05d4a3a24f05c2e450559f
clk: imx: fix pll clock parents

pllx_bypass_src mux shouldn't be the parent of pllx clock
since it's only valid when when pllx BYPASS bit is set.
Thus it is actually one parent of pllx_bypass only.

Instead, pllx parent should be fixed to osc according to
reference manual.
Other plls have the same issue.

e.g. before fix, the pll tree is:
osc                                      6            6    24000000          0 0
   pll1_bypass_src                       0            0    24000000          0 0
      pll1                               0            0   792000000          0 0
         pll1_bypass                     0            0   792000000          0 0
            pll1_sys                     0            0   792000000          0 0

After the fix, it's:
osc                                      6            6    24000000          0 0
   pll1                                  0            0   792000000          0 0
      pll1_bypass                        0            0   792000000          0 0
         pll1_sys                        0            0   792000000          0 0

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
drivers/clk/imx/clk-imx6q.c
drivers/clk/imx/clk-imx6sl.c
drivers/clk/imx/clk-imx6sx.c
drivers/clk/imx/clk-imx6ul.c
drivers/clk/imx/clk-imx7d.c