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(parent: de9f2c9) | patch
spi: synquacer: simplify tx completion checking
authorMasahisa Kojima <masahisa.kojima@linaro.org>
Tue, 17 May 2022 08:41:39 +0000 (17:41 +0900)
committerTom Rini <trini@konsulko.com>
Fri, 10 Jun 2022 17:37:32 +0000 (13:37 -0400)
commitf81aaa0b33bec4292838e75d14a0653775aea45d
tree5e5e53f7ec2e17ec8785f3dfd914b03638a44da2tree | snapshot
parentde9f2c9c2ed8ee4ffadc3909a46c17888fed619fcommit | diff
spi: synquacer: simplify tx completion checking

There is a TX-FIFO and Shift Register empty(TFES) status
bit in spi controller. This commit checks the TFES bit
to wait the TX transfer completes.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
drivers/spi/spi-synquacer.c diff | blob | history
Domain: System / Kernel;