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arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe
authorBharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Mon, 30 Jan 2017 06:36:02 +0000 (12:06 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 28 Nov 2017 15:09:09 +0000 (16:09 +0100)
commitf811eca9db05fc89fe52141b256231ff94859add
treeb5be64c6e74426bddbeb5ba48705dee42846f7b9tree | snapshot
parentd801ce553e84fded21060804f577b944da445317commit | diff
arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe

- Enabling GTR lane-0 to PCIe
- Enabling PCIe node in device tree

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/dts/zynqmp-zcu102-revA.dts diff | blob | history
Domain: System / Kernel;