drm/amd/display: Do not set DRR on pipe Commit
authorWesley Chalmers <Wesley.Chalmers@amd.com>
Fri, 4 Nov 2022 02:29:31 +0000 (22:29 -0400)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 22 Mar 2023 12:34:01 +0000 (13:34 +0100)
commitf8080f1e300e7abcc03025ec8b5bab69ae98daaa
tree3fbb02d09f2e1a8b8a401877aa30743a9717426c
parent20f8225ae7f4bf9c30f40705f036a9a7ba8f1bd6
drm/amd/display: Do not set DRR on pipe Commit

commit 56574f89dbd84004c3fd6485bcaafb5aa9b8be14 upstream.

[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.

Cc: stable@vger.kernel.org
Cc: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c