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(parent: fd9310f) | patch
freedreno/regs: add bit to control continuous clock with 7nm PHYs
authorDmitry Baryshkov <dbaryshkov@gmail.com>
Mon, 7 Jun 2021 13:14:39 +0000 (16:14 +0300)
committerMarge Bot <eric+marge@anholt.net>
Sun, 8 Aug 2021 20:15:42 +0000 (20:15 +0000)
commitf800b9182b9d82685c6a43471c681142ff5bba62
tree5ad3e130d4f1bf12566ef7e23b3921c47cc37f92tree | snapshot
parentfd9310f885f745a4294368f59ff025b0978bbdedcommit | diff
freedreno/regs: add bit to control continuous clock with 7nm PHYs

7nm PHYs need another special bit set in DSI_LANE_CTRL to enable
continuous DSI clock. Document this bit.

Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11219>
src/freedreno/registers/dsi/dsi.xml diff | blob | history
Domain: Graphics System / GL;