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(parent: 5c3b471) | patch
radv: always clear the SR0/SR1 bits of the HTILE buffer
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Wed, 9 Dec 2020 16:28:40 +0000 (17:28 +0100)
committerMarge Bot <eric+marge@anholt.net>
Tue, 5 Jan 2021 12:10:11 +0000 (12:10 +0000)
commitf7f6e9ad56df4f41a4dd9f4344b298ae17f25ad1
tree6b9335f6121c9706e626b1a28c57759225f24b99tree | snapshot
parent5c3b471c9f4b611a0a78c8c3f9534f8e7da8cbeccommit | diff
radv: always clear the SR0/SR1 bits of the HTILE buffer

To make sure the stencil compare state is properly initialized and
cleared when the driver performs a fast depth clear.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8039>
src/amd/vulkan/radv_cmd_buffer.c diff | blob | history
src/amd/vulkan/radv_meta_clear.c diff | blob | history
src/amd/vulkan/radv_meta_resolve_cs.c diff | blob | history
Domain: Graphics System / GL;