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clk: tegra: dfll: round down voltages based on alignment
authorJoseph Lo <josephl@nvidia.com>
Fri, 4 Jan 2019 03:06:50 +0000 (11:06 +0800)
committerThierry Reding <treding@nvidia.com>
Wed, 6 Feb 2019 13:29:08 +0000 (14:29 +0100)
commitf7ebf8874c2abb12be786fe73734ba47c87ff123
tree3f0ce27c8c84f918b81b4df7fc179b9f25f1db1dtree | snapshot
parent36541f0499fe02541de8edbcb05e6536104b11d2commit | diff
clk: tegra: dfll: round down voltages based on alignment

When generating the OPP table, the voltages are round down with the
alignment from the regulator. The alignment should be applied for
voltages look up as well.

Based on the work of Penny Chiu <pchiu@nvidia.com>.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-dfll.c diff | blob | history
Domain: System / Kernel;