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author	Roman Lebedev <lebedev.ri@gmail.com>
	Mon, 12 Dec 2022 23:32:46 +0000 (02:32 +0300)
committer	Roman Lebedev <lebedev.ri@gmail.com>
	Tue, 13 Dec 2022 00:40:21 +0000 (03:40 +0300)
commit	f7cdcc288454edd1c778c26499a646d20767119c
tree	c7dca0390bf90d3991f727ce5a6ac27188b70b27	tree \| snapshot
parent	a98bdaa9c99ea1aa029eeaf2bd91c4794dd88c81	commit \| diff

[NFC][Codegen][X86] Revisit interleaved load codegen tests

This matches the coverage with the Costmodel tests,
adds stride 5/7/8, and improves AVX512 checks.

I *think* i've compressed check prefixes
as much as possible, but it's a bit hard to tell.
But hey, at one no longer has to fight against FileCheck+UTC :).

28 files changed:

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-2.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll	[new file with mode: 0644]	blob

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