ARM: vexpress/TC2: add support for CPU DVFS
authorSudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
Tue, 29 Oct 2013 12:18:37 +0000 (12:18 +0000)
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>
Tue, 29 Oct 2013 23:48:25 +0000 (00:48 +0100)
commitf7cd2d835e0f17cde2e5cead92be0099d7e92a7c
tree99fdd746006029a5683c4e671ea134ad01cdba3a
parentad7722dab7292dbc1c4586d701ac226b68122d39
ARM: vexpress/TC2: add support for CPU DVFS

SPC(Serial Power Controller) on TC2 also controls the CPU performance
operating points which is essential to provide CPU DVFS. The M3
microcontroller provides two sets of eight performance values, one set
for each cluster (CA15 or CA7). Each of this value contains the
frequency(kHz) and voltage(mV) at that performance level. It expects
these performance level to be passed through the SPC PERF_LVL registers.

This patch adds support to populate these performance levels from M3,
build the mapping to CPU OPPs at the boot and then use it to get and
set the CPU performance level runtime.

Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Pawel Moll <Pawel.Moll@arm.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
arch/arm/mach-vexpress/Kconfig
arch/arm/mach-vexpress/Makefile
arch/arm/mach-vexpress/spc.c
arch/arm/mach-vexpress/spc.h
arch/arm/mach-vexpress/tc2_pm.c