review.tizen.org Git - platform/upstream/coreclr.git/commit

projects / platform / upstream / coreclr.git / commit

author	Tanner Gooding <tagoo@outlook.com>
	Thu, 7 Jun 2018 01:24:04 +0000 (18:24 -0700)
committer	GitHub <noreply@github.com>
	Thu, 7 Jun 2018 01:24:04 +0000 (18:24 -0700)
commit	f7993ddfc19ccce311df69b32f675bd076935e7f
tree	87921d580a0a4f22a7838aa426488f73347ce2ee	tree \| snapshot
parent	dce3234ecd057e7332140e137e23b0fe2aca9919	commit \| diff

Adding containment support for more x86 hardware intrinsics (#18297)

* Adding containment support to one-operand scalar HWIntrinsics (x86)

* Adding containment support to two-operand imm HWIntrinsics (x86)

* Adding containment support to three-operand imm HWIntrinsics (x86)

* Updating hwintrinsiccodegenxarch to properly mask Sse41.Insert for TYP_FLOAT

* Updating the Sse41.Insert tests for TYP_FLOAT

* Adding containment support for Sse2.CompareLessThan and BlendVariable (Sse41/Avx/Avx2)

* Fixing `genHWIntrinsic_R_RM_I` to call `emitIns_SIMD_R_R_I`, rather than `emitIns_R_R_I`

* Updating emitOutputSV to not modify the code for IF_RWR_RRD_SRD_CNS

* Cleaning up some of the emitxarch code.

* Moving roundps and roundpd into the IsDstSrcImm check

34 files changed:

src/jit/codegenlinear.h		diff \| blob \| history
src/jit/emitfmtsxarch.h		diff \| blob \| history
src/jit/emitxarch.cpp		diff \| blob \| history
src/jit/emitxarch.h		diff \| blob \| history
src/jit/hwintrinsiccodegenxarch.cpp		diff \| blob \| history
src/jit/lowerxarch.cpp		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Shared/GenerateTests.csx		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Byte.1.cs		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Byte.129.cs		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Int32.1.cs		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Int32.129.cs		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Int64.1.cs		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Int64.129.cs		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.SByte.1.cs		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.SByte.129.cs		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Single.0.cs		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Single.1.cs	[new file with mode: 0644]	blob
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Single.128.cs	[new file with mode: 0644]	blob
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Single.129.cs	[new file with mode: 0644]	blob
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Single.16.cs	[new file with mode: 0644]	blob
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Single.192.cs	[new file with mode: 0644]	blob
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Single.2.cs	[new file with mode: 0644]	blob
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Single.32.cs	[new file with mode: 0644]	blob
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Single.4.cs	[new file with mode: 0644]	blob
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Single.48.cs	[new file with mode: 0644]	blob
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Single.64.cs	[new file with mode: 0644]	blob
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Single.8.cs	[new file with mode: 0644]	blob
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.UInt32.1.cs		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.UInt32.129.cs		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.UInt64.1.cs		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.UInt64.129.cs		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Program.Sse41.cs		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Sse41_r.csproj		diff \| blob \| history
tests/src/JIT/HardwareIntrinsics/X86/Sse41/Sse41_ro.csproj		diff \| blob \| history

Domain: Dotnet / Core;

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