mmc: dcache: allocate cache aligned buffer for scr and switch_status
authorAnton staaf <robotboy@chromium.org>
Mon, 3 Oct 2011 13:54:59 +0000 (13:54 +0000)
committerWolfgang Denk <wd@denx.de>
Tue, 25 Oct 2011 07:25:13 +0000 (09:25 +0200)
commitf781dd383a0a28930612d48df11ccb2f3bca4eaa
treec67ef781efeaa228695575a92a29018c981d6dda
parent96d21237ec2b799f60a827ea680594b7ebfdac7f
mmc: dcache: allocate cache aligned buffer for scr and switch_status

Currently the sd_change_freq function allocates two buffers on the
stack that it passes down to the MMC device driver.  These buffers
could be unaligned to the L1 dcache line size.  This causes problems
when using DMA and with caches enabled.

This patch correctly cache alignes the buffers used for reading the
scr register and switch status values from an MMC device.

Change-Id: Ifa8414f572ef907681bd2d5ff3950285a215357d
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Mike Frysinger <vapier@gentoo.org>
drivers/mmc/mmc.c