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drm/i915: Read C0DRB3/C1DRB3 as 16 bits again
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 21 Apr 2021 15:33:59 +0000 (18:33 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 26 Apr 2021 20:56:34 +0000 (23:56 +0300)
commitf765a5b48c667bdada5e49d5e0f23f8c0687b21b
tree0a3a3475eac7bd4f20d42a1e795e1aaffb692355tree | snapshot
parented52c62d386f764194e0184fdb905d5f24194caecommit | diff
drm/i915: Read C0DRB3/C1DRB3 as 16 bits again

We've defined C0DRB3/C1DRB3 as 16 bit registers, so access them
as such.

Fixes: 1c8242c3a4b2 ("drm/i915: Use unchecked writes for setting up the fences")
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210421153401.13847-3-ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c diff | blob | history
Domain: System / Kernel;