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(parent: 2b045c5) | patch
fix hardware-makefile for osx, bugfix chisel-RegFile, and rename driver (#3371)
authorLuis Vega <vegaluisjose@users.noreply.github.com>
Fri, 14 Jun 2019 08:01:00 +0000 (01:01 -0700)
committereqy <eddieyan101@gmail.com>
Fri, 14 Jun 2019 08:01:00 +0000 (01:01 -0700)
commitf731e0e666ff07ceba228e2ea0b1bcda837fa6e1
tree3a4c4ef7d7f557d6011aca913dd68cc180390b47tree | snapshot
parent2b045c560a7bac6852affb2ed5fc9df550405a2fcommit | diff
fix hardware-makefile for osx, bugfix chisel-RegFile, and rename driver (#3371)
vta/apps/tsim_example/Makefile diff | blob | history
vta/apps/tsim_example/hardware/chisel/Makefile diff | blob | history
vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala diff | blob | history
vta/apps/tsim_example/hardware/verilog/Makefile diff | blob | history
vta/apps/tsim_example/python/__init__.py [new file with mode: 0644] blob
vta/apps/tsim_example/python/accel/__init__.py [deleted file] blob | history
vta/apps/tsim_example/python/tsim.py [moved from vta/apps/tsim_example/python/accel/driver.py with 90% similarity] diff | blob | history
vta/apps/tsim_example/tests/python/chisel_accel.py diff | blob | history
vta/apps/tsim_example/tests/python/verilog_accel.py diff | blob | history
vta/hardware/chisel/Makefile diff | blob | history
Domain: Machine Learning / ML Framework;