gpu: ipu-v3: limit pixel clock divider to 8-bits
authorPhilipp Zabel <p.zabel@pengutronix.de>
Tue, 10 Mar 2015 14:03:43 +0000 (15:03 +0100)
committerPhilipp Zabel <p.zabel@pengutronix.de>
Tue, 31 Mar 2015 10:03:54 +0000 (12:03 +0200)
commitf7089d923eacb9c8e57d8492699662756881b54d
tree9751d3e0c1daed286261d150b961e9b81be99bd1
parent91fd89660ba2e8ee59a587294fa9b17761691b05
gpu: ipu-v3: limit pixel clock divider to 8-bits

The DI pixel clock divider bit field is only 8 bits wide for the
integer part, so limit the divider to the 1...255 interval before
deciding whether the internal clock can be used and before writing
to the register.

Reported-by: Felix Mellmann <felix.mellmann@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
drivers/gpu/ipu-v3/ipu-di.c