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[RISCV] Teach lowerSPLAT_VECTOR_PARTS to detect cases where Hi is sign extended from Lo.
authorCraig Topper <craig.topper@sifive.com>
Thu, 22 Apr 2021 03:15:39 +0000 (20:15 -0700)
committerCraig Topper <craig.topper@sifive.com>
Thu, 22 Apr 2021 03:24:23 +0000 (20:24 -0700)
commitf6d8cf7798440f303d5a273999e6647cbe795ac6
tree202f97326d81ad95eaca3584927aae04ebd23ecetree | snapshot
parent77ca2a689368e3a27a72b432ab93c9c352d73073commit | diff
[RISCV] Teach lowerSPLAT_VECTOR_PARTS to detect cases where Hi is sign extended from Lo.

This recognizes the case when Hi is (sra Lo, 31). We can use
SPLAT_VECTOR_I64 rather than splatting the high bits and
combining them in the vector register.
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll diff | blob | history
Domain: System / Toolchain;