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(parent: c0eb4de) | patch
Fix R0 use in PowerPC VSX store for FastIsel.
authorSamuel Antao <sfantao@us.ibm.com>
Tue, 17 Mar 2015 15:00:57 +0000 (15:00 +0000)
committerSamuel Antao <sfantao@us.ibm.com>
Tue, 17 Mar 2015 15:00:57 +0000 (15:00 +0000)
commitf68156015dd0596ffc94385c163ee4d32efb15f2
tree766a4303d1934ef02efa48b83da51b661390faeftree | snapshot
parentc0eb4de58d766de2ca759943f8d080aa1ae32dcbcommit | diff
Fix R0 use in PowerPC VSX store for FastIsel.

The VSX stores are sometimes generated with a undefined index register, causing %noreg to be used and R0 to be emitted later on. The semantics of the VSX store (e.g. stdsdx) requires R0 to be used as base if we want zero to be used in the computation of the effective address instead of the content of R0. This patch checks if no index register was generated and forces R0 to be used as base address.

llvm-svn: 232486
llvm/lib/Target/PowerPC/PPCFastISel.cpp diff | blob | history
llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll [new file with mode: 0644] blob
Domain: System / Toolchain;