drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 11 Feb 2014 17:52:06 +0000 (19:52 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 11 Feb 2014 22:00:47 +0000 (23:00 +0100)
commitf66fab8e1cd6b3127ba4c5c0d11539fbe1de1e36
tree13024a866349329c4940784f46cc03bae02d9184
parent753b1ad4a281b0663329409d410243e91825c323
drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB

According to BSpec the entire MI_DISPLAY_FLIP packet must be contained
in a single cacheline. Make sure that happens.

v2: Use intel_ring_begin_cacheline_safe()
v3: Use intel_ring_cacheline_align() (Chris)

Cc: Bjoern C <lkml@call-home.ch>
Cc: Alexandru DAMIAN <alexandru.damian@intel.com>
Cc: Enrico Tagliavini <enrico.tagliavini@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74053
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c