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(parent: b10ef0f) | patch
drm/vc4: Correct interrupt masking bit assignment for HVS5
authorDave Stevenson <dave.stevenson@raspberrypi.com>
Thu, 11 Aug 2022 14:52:28 +0000 (15:52 +0100)
committerPhil Elwell <8911409+pelwell@users.noreply.github.com>
Thu, 1 Sep 2022 16:58:41 +0000 (17:58 +0100)
commitf64b5666e11dce481737208027d4af300c63842d
treecb670daa9a1d72765462a3160576562e1629e1d2tree | snapshot
parentb10ef0fdec9c082cc1ba9512e2846a3d936f96e6commit | diff
drm/vc4: Correct interrupt masking bit assignment for HVS5

HVS5 has moved the interrupt enable bits around within the
DISPCTRL register, therefore the configuration has to be updated
to account for this.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
drivers/gpu/drm/vc4/vc4_hvs.c diff | blob | history
drivers/gpu/drm/vc4/vc4_regs.h diff | blob | history
Domain: System / Kernel;