[ARM] Add ARMISD::VLD1DUP to match vld1_dup more consistently.
authorEli Friedman <efriedma@codeaurora.org>
Fri, 16 Dec 2016 18:44:08 +0000 (18:44 +0000)
committerEli Friedman <efriedma@codeaurora.org>
Fri, 16 Dec 2016 18:44:08 +0000 (18:44 +0000)
commitf624ec27b75701f1227eb03a44f3da84920c798d
treed10b422365e2b461b34e1a53f1f29a72cb5b5b00
parent79b4f0ad9cc5b019cf71bac388f1da1de4dd4e34
[ARM] Add ARMISD::VLD1DUP to match vld1_dup more consistently.

Currently, there are substantial problems forming vld1_dup even if the
VDUP survives legalization. The lack of an actual node
leads to terrible results: not only can we not form post-increment vld1_dup
instructions, but we form scalar pre-increment and post-increment
loads which force the loaded value into a GPR. This patch fixes that
by combining the vdup+load into an ARMISD node before DAGCombine
messes it up.

Also includes a crash fix for vld2_dup (see testcase @vld2dupi8_postinc_variable).

Recommiting with fix to avoid forming vld1dup if the type of the load
doesn't match the type of the vdup (see
https://llvm.org/bugs/show_bug.cgi?id=31404).

Differential Revision: https://reviews.llvm.org/D27694

llvm-svn: 289972
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.h
llvm/test/CodeGen/ARM/vlddup.ll
llvm/test/CodeGen/ARM/vmul.ll