[RISCV] Add vendor-defined XTheadCmo (Cache Management Operations) extension
authorManolis Tsamis <manolis.tsamis@vrull.eu>
Wed, 22 Feb 2023 09:36:42 +0000 (10:36 +0100)
committerPhilipp Tomsich <philipp.tomsich@vrull.eu>
Wed, 22 Feb 2023 09:57:48 +0000 (10:57 +0100)
commitf5b484c56f7b0bbf265c06de70ed0c432543847f
tree213ed229fd0f000f44a729126fbe8e1260ed2325
parentabc1f3329831606b06a934bba8ac3fc3df522e07
[RISCV] Add vendor-defined XTheadCmo (Cache Management Operations) extension

The vendor-defined XTHeadCmo (there are some similarities with the
Zicbom standard extension) extension adds cache management instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=a9ba8bc2d396fb8ae2b892f3bc6be8cdfe4b555c

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144496
llvm/docs/RISCVUsage.rst
llvm/docs/ReleaseNotes.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/xtheadcmo-invalid.s [new file with mode: 0644]
llvm/test/MC/RISCV/xtheadcmo-valid.s [new file with mode: 0644]