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[RISCV] Teach needVSETVLIPHI to handle mask register instructions.
authorCraig Topper <craig.topper@sifive.com>
Mon, 15 Nov 2021 17:49:22 +0000 (09:49 -0800)
committerCraig Topper <craig.topper@sifive.com>
Mon, 15 Nov 2021 17:57:28 +0000 (09:57 -0800)
commitf59307bfdc01c584bfa7cd31a55226831bf5590f
tree7e90e6b050b64b222ad4bf29a0c2f1ef9bfa7427tree | snapshot
parent4f11944652dec790c56e029d9a207db284831479commit | diff
[RISCV] Teach needVSETVLIPHI to handle mask register instructions.

This handles the case where the mask register instruction input
comes from a Phi of vsetvlis. If the VLMAX is the same as the VLMAX
required by the mask register instruction, we can avoid a vsetvli.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D113204
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp diff | blob | history
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll diff | blob | history
Domain: System / Toolchain;