RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.

RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.

gcc/ChangeLog:

	* config.gcc: Add riscv-vector-builtins-bases.o and riscv-vector-builtins-shapes.o
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_I_OPS): New macro.
	(DEF_RVV_FUNCTION): Ditto.
	(handle_pragma_vector): Add intrinsic framework.
	* config/riscv/riscv.cc (riscv_print_operand): Add operand print for vsetvl/vsetvlmax.
	* config/riscv/riscv.md: include vector.md.
	* config/riscv/t-riscv: Add riscv-vector-builtins-bases.o and riscv-vector-builtins-shapes.o
	* config/riscv/riscv-vector-builtins-bases.cc: New file.
	* config/riscv/riscv-vector-builtins-bases.h: New file.
	* config/riscv/riscv-vector-builtins-functions.def: New file.
	* config/riscv/riscv-vector-builtins-shapes.cc: New file.
	* config/riscv/riscv-vector-builtins-shapes.h: New file.
	* config/riscv/riscv-vector-builtins-types.def: New file.
	* config/riscv/vector.md: New file.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/vsetvl-1.c: New test.