radv: don't even attempt to prefetch on SI
authorGrazvydas Ignotas <notasas@gmail.com>
Sat, 10 Jun 2017 15:34:22 +0000 (18:34 +0300)
committerGrazvydas Ignotas <notasas@gmail.com>
Sun, 11 Jun 2017 11:28:40 +0000 (14:28 +0300)
commitf56aa25ac5d2509392177bfa503aa52a565b9a85
tree4a2f9bb49a06b35f1db8d6b310b69ae34f657dcb
parentf490200973a233454158ff191f279d45be3b39c0
radv: don't even attempt to prefetch on SI

Before bcae327469 this was emitting CP DMA packet even on SI, but
apparently hasn't caused too many problems. After that commit the
CP DMA code now always sets the CIK+ only bit for prefetch. Just
follow radeonsi there and don't try to prefetch at all.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101334
Fixes: bcae327469 "radv: realign cp dma code with radeonsi"
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
src/amd/vulkan/radv_cmd_buffer.c