[AArch64][SVE] Instcombine SVE LD1/ST1 to stock LLVM IR
authorMatt Devereau <matthew.devereau@arm.com>
Thu, 4 Nov 2021 16:10:55 +0000 (16:10 +0000)
committerMatt Devereau <matthew.devereau@arm.com>
Tue, 16 Nov 2021 11:10:23 +0000 (11:10 +0000)
commitf526c600c043d9e83a359e79d617077d947c1dc3
tree8c46f5af40ca51c73c7cf0e5a8cafdde6765628a
parent3f3d4e8a15a7cc3be1bf071e0a581b60143702e1
[AArch64][SVE] Instcombine SVE LD1/ST1 to stock LLVM IR

InstCombine AArch64 LD1/ST1 to llvm.masked.load/llvm.masked.store
and LD1/ST1 to load/store when a ptrue all predicate pattern operand
is present.

This allows existing IR optimizations such as dead-load removal to
occur.

Differential Revision: https://reviews.llvm.org/D113489
15 files changed:
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sb.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sh.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sw.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ub.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uh.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uw.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1h.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1w.c
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-loadstore.ll [new file with mode: 0644]