AMDGPU/GlobalISel: Fix bit ops for non-power-of-2 sizes
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 25 Feb 2019 21:32:48 +0000 (21:32 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 25 Feb 2019 21:32:48 +0000 (21:32 +0000)
commitf4bfe4cd178e09d3ceafb613fb61a70ba845cab8
tree6a52cca6faaaae96a0af337d23d6442126b0be91
parent0a3fe502e6451941eaebc9911a4c7043334b7fb4
AMDGPU/GlobalISel: Fix bit ops for non-power-of-2 sizes

llvm-svn: 354825
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir