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irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed
authorBrendan Higgins <brendanhiggins@google.com>
Sat, 3 Jun 2017 01:29:49 +0000 (18:29 -0700)
committerMarc Zyngier <marc.zyngier@arm.com>
Thu, 22 Jun 2017 13:15:00 +0000 (14:15 +0100)
commitf48e699ddf7056f83bb8e2dbe3c2ae8d1ff1a31a
treeacdac0e97e8286bee1ebdb30e21aa8f8e9013a1etree | snapshot
parent0a56f9eebe6320980b68c60c852436cbf2a14b61commit | diff
irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed

The Aspeed 24XX/25XX chips share a single hardware interrupt across 14
separate I2C busses. This adds a dummy irqchip which maps the single
hardware interrupt to software interrupts for each of the busses.

Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
drivers/irqchip/Makefile diff | blob | history
drivers/irqchip/irq-aspeed-i2c-ic.c [new file with mode: 0644] blob
Domain: System / Kernel;