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arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1}
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Mon, 2 Jan 2023 22:18:15 +0000 (22:18 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 26 Jan 2023 15:03:03 +0000 (16:03 +0100)
commitf4673e52dbab9d890d236ed75264653bcd43bac1
tree69349a84177d8f2d0636aa3c630400ddd71cb1c7tree | snapshot
parent85169df721078bf90fb0fc3bf15e4743fea45b2dcommit | diff
arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1}

The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and
ETH1 respectively.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230102221815.273719-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi diff | blob | history
Domain: System / Kernel;