[X86][Costmodel] Load/store i32/f32 Stride=2 VF=2 interleaving costs
authorRoman Lebedev <lebedev.ri@gmail.com>
Fri, 1 Oct 2021 13:52:36 +0000 (16:52 +0300)
committerRoman Lebedev <lebedev.ri@gmail.com>
Fri, 1 Oct 2021 14:48:13 +0000 (17:48 +0300)
commitf44d9009c25827dd9fad5bfa240f6e59335d07b8
tree3cec6a40fc67fb7764d8ebda60483e554213dbe0
parent4f0a39b9b4ba67f26497688f831294e522eb53a5
[X86][Costmodel] Load/store i32/f32 Stride=2 VF=2 interleaving costs

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/4rY96hnGT - for intels `Block RThroughput: =2.0`; for ryzens, `Block RThroughput: =1.0`
So pick cost of `2`.

For store we have:
https://godbolt.org/z/vbo37Y3r9 - for intels `Block RThroughput: =1.0`; for ryzens, `Block RThroughput: =0.5`
So pick cost of `1`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D110753
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll
llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll
llvm/test/Transforms/LoopVectorize/X86/interleaving.ll