[SVE] Change definition of reduction ISD nodes to have an SVE vector result type.
authorPaul Walker <paul.walker@arm.com>
Thu, 17 Sep 2020 11:04:35 +0000 (12:04 +0100)
committerPaul Walker <paul.walker@arm.com>
Mon, 21 Sep 2020 12:16:28 +0000 (13:16 +0100)
commitf3fa954b5b19acdd4b95ff2ca1ff4f74f4b6b21b
treee1e3b9f4c249baa1facb7aa74b1b61d7ac705783
parent6457455248d5b83a7e4274f06b6313b15cd51421
[SVE] Change definition of reduction ISD nodes to have an SVE vector result type.

The current nodes, AArch64::SMAXV_PRED for example, are defined to
return a NEON vector result.  This is incorrect because they modify
the complete SVE register and are thus changed to represent such.

This patch also adds nodes for UADDV_PRED and SADDV_PRED, which
unifies the handling of all SVE reductions.

NOTE: Floating-point reductions are already implemented correctly,
so this patch is essentially making everything consistent with those.

Differential Revision: https://reviews.llvm.org/D87843
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/CodeGen/AArch64/sve-int-reduce-pred.ll