x86/microcode: Use native CPUID to tickle out microcode revision
authorBorislav Petkov <bp@suse.de>
Mon, 9 Jan 2017 11:41:44 +0000 (12:41 +0100)
committerThomas Gleixner <tglx@linutronix.de>
Mon, 9 Jan 2017 22:11:14 +0000 (23:11 +0100)
commitf3e2a51f568d9f33370f4e8bb05669a34223241a
treef9a55874706d07e78e8472433074d1e1fe4ee11f
parent5dedade6dfa243c130b85d1e4daba6f027805033
x86/microcode: Use native CPUID to tickle out microcode revision

Intel supplies the microcode revision value in MSR 0x8b
(IA32_BIOS_SIGN_ID) after CPUID(1) has been executed. Execute it each
time before reading that MSR.

It used to do sync_core() which did do CPUID but

  c198b121b1a1 ("x86/asm: Rewrite sync_core() to use IRET-to-self")

changed the sync_core() implementation so we better make the microcode
loading case explicit, as the SDM documents it.

Reported-and-tested-by: Jun'ichi Nomura <j-nomura@ce.jp.nec.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: http://lkml.kernel.org/r/20170109114147.5082-3-bp@alien8.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
arch/x86/kernel/cpu/intel.c
arch/x86/kernel/cpu/microcode/intel.c