[DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal
authorCraig Topper <craig.topper@intel.com>
Tue, 24 Apr 2018 22:35:27 +0000 (22:35 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 24 Apr 2018 22:35:27 +0000 (22:35 +0000)
commitf3cefad255e9ff56bead504ed787379d735760fc
tree5ab4ae9edfb10a8fa4417c936473581a1c006a21
parent07b0059083f2df678f0bb7d1a8f7b810bc854bdc
[DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal

We were previously prefering ZEXTLOAD over EXTLOAD if it is legal. This triggers during X86's promotion of i16->i32. Not sure about other targets.

Using ZEXTLOAD can prevent folding it to SEXTLOAD later if we were to promote a sign extended operand like we would need for SRA. However, X86 doesn't currently promote i16 SRA. I was looking into doing that which is how I found this issue.

This is also blocking our ability to fold 4 byte aligned EXTLOADs with "loadi32". This is what caused most of the test changes here.

Differential Revision: https://reviews.llvm.org/D45585#inline-402825

llvm-svn: 330781
13 files changed:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/X86/3addr-16bit.ll
llvm/test/CodeGen/X86/avx512-mask-op.ll
llvm/test/CodeGen/X86/fixup-bw-copy.ll
llvm/test/CodeGen/X86/iabs.ll
llvm/test/CodeGen/X86/ins_subreg_coalesce-1.ll
llvm/test/CodeGen/X86/mul-constant-i16.ll
llvm/test/CodeGen/X86/popcnt.ll
llvm/test/CodeGen/X86/pr32345.ll
llvm/test/CodeGen/X86/pr32420.ll
llvm/test/CodeGen/X86/pr34137.ll
llvm/test/CodeGen/X86/promote-i16.ll
llvm/test/CodeGen/X86/reduce-trunc-shl.ll