projects / platform / kernel / linux-starfive.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 9430ff3) | patch
ARM: dts: at91: sama7g5-ek: use blocks 0 and 1 of TCB0 as cs and ce
authorClaudiu Beznea <claudiu.beznea@microchip.com>
Wed, 20 Oct 2021 09:46:56 +0000 (12:46 +0300)
committerNicolas Ferre <nicolas.ferre@microchip.com>
Thu, 21 Oct 2021 11:45:16 +0000 (13:45 +0200)
commitf3c0366411d6893360be21a7544595bf275bc9b2
tree1270cc90e378dc5a9780a99c66af95ad02f82039tree | snapshot
parent9430ff34385e285984711fccb2226771cbc675fbcommit | diff
ARM: dts: at91: sama7g5-ek: use blocks 0 and 1 of TCB0 as cs and ce

Use blocks 0 and 1 of TCB0 for clocksource and clockevent functionality.
PIT64B is already enabled on SAMA7G5 targets for this but TCB0 will be
used as a fallback only in case PIT64B will fail to probe.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211020094656.3343242-4-claudiu.beznea@microchip.com
arch/arm/boot/dts/at91-sama7g5ek.dts diff | blob | history
Domain: System / Kernel;