[RISCV][InsertVSETVLI] Relax tail policy more often for vmv.s.x
authorLuke Lau <luke@igalia.com>
Wed, 31 May 2023 17:04:25 +0000 (17:04 +0000)
committerLuke Lau <luke@igalia.com>
Wed, 31 May 2023 17:18:44 +0000 (18:18 +0100)
commitf3b39ceaf535af142f392720b86952bcefe9f314
treeaf7b37fa48201ba435f5da9488698967317cc7a8
parentbadf11de4ac63081180893aa757bbafd1e672132
[RISCV][InsertVSETVLI] Relax tail policy more often for vmv.s.x

If a vm.s.x pseudo has an undef passthru operand, then we're free to use
whatever tail policy we want for VL > 1. We previously relaxed the tail
policy for this but only when we could also expand the SEW.
This patch changes it to relax the tail policy even if the SEW can't be
expanded and removes a few more toggles, as well as fully moving the
vmv.s.x logic into getDemanded.
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
llvm/test/CodeGen/RISCV/rvv/insertelt-fp.ll
llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll