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(parent: 7acf89a) | patch
AMDGPU/GlobalISel: RegBankSelect some simple operations
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 13 Dec 2018 08:23:51 +0000 (08:23 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 13 Dec 2018 08:23:51 +0000 (08:23 +0000)
commitf38f483bef6478b85d66769694c9077a0ae10967
treee3b71cfd24257af670b8b05be0a61461a133ac5atree | snapshot
parent7acf89a21a543dd361a3ff47b50e65228e520a01commit | diff
AMDGPU/GlobalISel: RegBankSelect some simple operations

llvm-svn: 349012
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir [new file with mode: 0644] blob
Domain: System / Toolchain;