[X86] Add WriteBitScan/WriteLZCNT/WriteTZCNT/WritePOPCNT scheduler classes (PR36881)
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 26 Mar 2018 18:19:28 +0000 (18:19 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 26 Mar 2018 18:19:28 +0000 (18:19 +0000)
commitf33d9052935869fb2b70272b41de5b5df610c958
tree1e64db3a3965e27f5a8590916780b04426b7c0f8
parent7c4b5d92f14ac38eaae17f5e486c83bcdc87344b
[X86] Add WriteBitScan/WriteLZCNT/WriteTZCNT/WritePOPCNT scheduler classes (PR36881)

Give the bit count instructions their own scheduler classes instead of forcing them into existing classes.

These were mostly overridden anyway, but I had to add in costs from Agner for silvermont and znver1 and the Fam16h SoG for btver2 (Jaguar).

Differential Revision: https://reviews.llvm.org/D44879

llvm-svn: 328566
15 files changed:
llvm/lib/Target/X86/X86InstrInfo.td
llvm/lib/Target/X86/X86InstrSSE.td
llvm/lib/Target/X86/X86SchedBroadwell.td
llvm/lib/Target/X86/X86SchedHaswell.td
llvm/lib/Target/X86/X86SchedSandyBridge.td
llvm/lib/Target/X86/X86SchedSkylakeClient.td
llvm/lib/Target/X86/X86SchedSkylakeServer.td
llvm/lib/Target/X86/X86Schedule.td
llvm/lib/Target/X86/X86ScheduleBtVer2.td
llvm/lib/Target/X86/X86ScheduleSLM.td
llvm/lib/Target/X86/X86ScheduleZnver1.td
llvm/test/CodeGen/X86/bmi-schedule.ll
llvm/test/CodeGen/X86/lzcnt-schedule.ll
llvm/test/CodeGen/X86/popcnt-schedule.ll
llvm/test/CodeGen/X86/schedule-x86_64.ll