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drm/i915/d13: Add Wa_16015201720 disabling clock gating for PIPEDMC-A/B
authorImre Deak <imre.deak@intel.com>
Wed, 27 Jul 2022 16:45:23 +0000 (19:45 +0300)
committerImre Deak <imre.deak@intel.com>
Thu, 28 Jul 2022 13:52:56 +0000 (16:52 +0300)
commitf31bccd3989d504a0c90b4562908ea18162d7662
tree2fedb82c3fc2db1c43ba726922afdf7de5e968cftree | snapshot
parentfa6a4cdeafa0ab674d0f72067304c5408c89964fcommit | diff
drm/i915/d13: Add Wa_16015201720 disabling clock gating for PIPEDMC-A/B

Add a workaround making sure that PIPEDMC-A/B is enabled when the
firmware needs these on D13 platforms to save/restore the registers
backed by the PW_1 and PW_A power wells.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220727164523.1621361-2-imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_display_power.c diff | blob | history
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
Domain: System / Kernel;