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clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tue, 28 Sep 2021 13:01:32 +0000 (14:01 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 8 Oct 2021 13:08:35 +0000 (15:08 +0200)
commitf294a0ea9d12a658ff326bbe0d64137659bc2fc9
tree63692058ef702cbd0dd38676dc49a08f85afb9b5tree | snapshot
parentcc3e8f97bbd370b51b3bb7fec391d65d461d7d02commit | diff
clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller

Add clock and reset entries for SPI Multi I/O Bus Controller.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210928130132.15022-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | history
drivers/clk/renesas/rzg2l-cpg.h diff | blob | history
Domain: System / Kernel;