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(parent: aa30aae) | patch
ram: rk3399: Configure soc odt support
authorJagan Teki <jagan@amarulasolutions.com>
Tue, 16 Jul 2019 11:57:24 +0000 (17:27 +0530)
committerKever Yang <kever.yang@rock-chips.com>
Sat, 20 Jul 2019 15:59:44 +0000 (23:59 +0800)
commitf288d54936d7360e934132a128d7e92d3b1c95a0
tree45e1bf51b45e76cb67291b25057d41ae920f4188tree | snapshot
parentaa30aae8b4e8c871a263ad67c4b4fdca236bf7c1commit | diff
ram: rk3399: Configure soc odt support

CTL 145, 146, 159, 160 registers are used to configure
soc odt on rk3399.

These soc odt values are updated from CS0_MR22_VAL and
CS1_MR22_VAL and for lpddr4 these values ORed with
tsel_rd_select_n.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
drivers/ram/rockchip/sdram_rk3399.c diff | blob | history
Domain: System / Kernel;